This invention relates to multiprocessing systems which share a main storage and, more particularly, to a prefixing arrangement which permits each processor to selectively access blocks of data in the main storage.
Prefixing techiques have been used in multiprocessing systems as exemplified in U.S. Pat. No. 3,555,513 to E. A. Hauck et al issued Jan. 12, 1971 wherein storage address values from each processor are modified by a different constant amount so that each processor accesses an assigned portion of storage. Address limit control means are provided to prevent each processor from accessing the storage area assigned to the other processor. However, with the advent or more sophisticated multiprocessing systems and to provide more efficient utilization of main storage, it is necessary to not only commonly share storage but to also permit each processor to gain access to those portions of storage assigned to other processors in the system. Thus, in present day multiprocessing systems, main storage may be divided into areas which contain data and programs which are unique and private to each processor associated with the system and other areas which contain data which are common to all the processors of the system. Each unique area may be designated as a prefixed storage area (PSA) and may contain data and programs which are unique and private to that processor. The type of information contained in a PSA may include program and channel status words, a timer, interruption indicators, hardware diagnostic logouts, a private working storage area, temporary storage of general registers, interprocessor communication routines, error recovery routines, etc. Such a storage area may, for example, occupy 4096 (4K) bytes of storage and be assigned to a predetermined block of storage such as the first 4096 storage locations. For inter-processor communications and to minimize operator action, it is desirable, unlike the prior art system of the Hauck et al patent, to permit the active processor to have access to all blocks of storage including its own PSA and the PSA's assigned to the other processors in the system. Also, for efficient operation, it is desirable to have each processor provide the same reference block when the processor is to access its associated PSA which address is then relocated or not in accordance with the prefix number associated with the respective processor.
One arrangement that has been used for handling a shared storage dual processor system is the IBM System/360 Time Sharing System embodied in the IBM System/360 Model 67. In that system, each processor is assigned a unique 4K block of shared storage for its PSA. This is accomplished by assigning a different prefix value to each processor. Accordingly, each processor references its own PSA as storage locations 0 to 4K and the unique prefix value is directly added to the storage reference value thereby relocating the storage reference to the assigned PSA block. Each processor also references the PSA of the other processor by directly referencing the storage locations assigned to the PSA of the other processor. Thus, with this arrangement, the PSA block of each processor is indirectly referenced by forward prefixing the addresses in the 0 to 4K range and the PSA block of the other processor is directly referenced by its actual storage addresses. However, with this arrangement, the prefix values are not changeable other than by a hardwire change and storage locations 0 to 4K cannot be used since all references to those locations are relocated. Another arrangement that has been used for handling a shared storage dual processor system is the IBM System/360 Model 65 Multiprocessing System. In that system, only one of the two processors is assigned a prefix value, allowing storage locations 0 to 4K to be assigned to the non-prefixed processor. With this arrangement, the non-prefixed processor references its own PSA as storage locations 0 to 4K and the other processor's PSA as storage locations T-4K to T, where T represents the highest storage address in the system. On the other hand, the prefixed processor also logically references its own PSA as storage locations 0 to 4K but these references are relocated to the assigned PSA at storage locations T-4K to T. The prefixed processor also references to other processor's PSA as storage locations T-4K to T, but, in this case, the prefix value is subtracted by the storage reference value to relocate the storage references to storage locations 0 to 4K which is the PSA of the non-prefixed processor. Thus, with this arrangement, the prefixed processor uses a forward prefixing arrangement for accessing its own PSA and a reverse prefixing arrangement for accessing the PSA of the non-prefixed processor. Also, however, with this arrangement, one processor must always use storage locations 0 to 4K as its PSA and the prefix value for the other processor is not changeable other than by a hardwire change.
From the above, it should be clear that there are a number of limitations to the prior art approaches and that it is desirable to obtain the advantages of these approaches and yet minimize their disadvantages.